Numerous types of electronic devices make use of phase-locked loops (PLLs), wherein both analog and digital varieties of PLLs are known. Such devices include, for example, cellular telephones, radio transceivers, process controllers and other instrumentation, and so on. Phase-locked loops are often employed in frequency synthesis. Most advanced frequency synthesizers within RF communication systems have full digital implementations and are referred to as digital PLLs (DPLLs), or all-digital PLLs. The functional circuitries of a DPLL are designed as digital control blocks, wherein all internal signals between the different functional blocks of the PLL are digital in format.
One performance criteria of a DPLL is referred to as the “lock-in criterion” or “settling time”, and is defined by the time required for the DPLL to lock onto (i.e., stabilize at) a new operating frequency. Thus, the lock-in criterion refers to a transitory characteristic of the DPLL. Typically, DPLLs have a relatively limited “capture range”, or frequency range about the new operating point wherein the DPLL will positively lock (i.e., settle) once the digital controlled oscillator of the DPLL is shifted sufficiently toward the new operating frequency. It is desirable to achieve lock at the new operating frequency as quickly as possible.
FIG. 1 depicts a DPLL 100 in accordance with known techniques. The DPLL 100 includes a time-to-digital converter (TDC) 102, which serves to measure the time delay between the phase of a reference clock input (Fref) and the phase of a divided-by-N (wherein N is integer or fractional value) digital controlled oscillator (DCO) signal (Fv) 114. One of ordinary skill in the art will appreciate that in modern PLL frequency synthesizers, the integer divider ratio is changed every reference period by a sigma-delta modulator in order to generate a fractional divider ratio on an average. The output from the TDC 102 is a digital word 104 representing the phase- or time-error between the two signals Fref and Fv. The digital word 104 from the TDC 102 is filtered and processed by a digital loop filter (DLF) 106. The DLF 106 thus derives a frequency control word (FCW) 108 that is sent to a DCO 110. The FCW 108 represents an error between the instantaneous operating frequency and the newly desired operating frequency of the DCO 110. These operating parameters can be thought of in terms of classic control theory as “process variable” (i.e., present value) and “set point” (i.e., desired value), respectively. In any case, the DCO 110 responds to the FCW 108 and shifts its operating frequency accordingly toward the new operating point. In turn, the output frequency (Fdco) 116 of the DCO 110 is provided to a counter/divider 112 that divides the Fdco signal 116 by an integer or fractional “N” so as to derive the Fv signal 114 in accordance with equation 1 below:Fv=Fdco/N  (Equation 1)
The lock-in criterion depends on various system and circuit parameters such as, for example, the loop bandwidth of the loop filter, the gain of the DCO (e.g., 110), and the gain of the TDC (e.g., 102) in a purely digital implementation. The capture range of the TDC is also an important parameter regarding lock-in performance of a DPLL (e.g., 100). Typically, the phase detector in an analog PLL (not shown) is implemented as a phase frequency detector that has a phase sensitivity of one period of the reference frequency signal (e.g., Fref), and an unambiguous frequency selectivity—that is, the present operating frequency is either too high or too low. Such analog PLL's often operate in accordance with “Up” and “Down” signals in regard to shifting their operating frequency.
In contrast, presently used DPLLs include TDCs (e.g., 102) having limited measurement ranges for the time interval between the phases of the two input frequencies (e.g., Fref and Fv). Additionally, the TDC often has no frequency selectivity—that is, it cannot distinguish between “too high” and “too low” with respect to operating frequency error. The limited range is inherent in the design of a TDC because a large capture range can generally be reached only with a low time resolution. Conversely, a satisfactory time resolution is only feasible with a small capture range. Thus, a balancing of opposed TDC performance characteristics has been generally necessary. This capture range vs. time resolution relationship is expressed equation 2 below:φcapt·(Tref/2π)=tcapt<<Tref=1/Fref  (Equation 2)
Wherein:                φcapt is the span of the capture range in radians;        Tref is the period of the reference frequency in seconds;        tcapt is the span of the capture range in seconds; and        Fref is the reference frequency in cycles per second        
FIG. 2 is a time-to-digital converter (TDC) 200 in accordance with one known approach for dealing with the limited capture range characteristics of typical DPLLs. The TDC 200 receives a reference frequency signal Fref and divided-by-N oscillator signal Fv as respectively introduced above. The TDC 200 then derives a time difference (or error) output signal 202 analogous to signal 104 above. The TDC 200 further provides an out-of-measurement-range output signal 204 that, depending on value, indicates an in- or out-of-capture-range state for the TDC 200. This signal 204 is then used to trigger and/or control additional lock-in measures that are used within the corresponding DPLL (not shown).
FIG. 3 is a signal diagram 300 depicting input vs. output signal performance of a TDC (e.g., 200) having a restricted operating or capture range. As shown, there is a substantially linear relationship between the measured time difference between the Fref and Fv input signals, and the time difference output signal provided by the TDC. Furthermore, the time difference output signal varies, or “swings”, over a limited predetermined range wherein a constant-level output signal is provided once the time error between the two input signals Fref and Fv exceeds some tmax threshold.